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LTC3404 1.4MHz High Efficiency Monolithic Synchronous Step-Down Regulator
FEATURES
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DESCRIPTIO
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High Efficiency: Up to 95% Very Low Quiescent Current: Only 10A During Operation 600mA Output Current at VIN = 3.3V 2.65V to 6V Input Voltage Range 1.4MHz Constant Frequency Operation Synchronizable from 1MHz to 1.7MHz Selectable Burst ModeTM Operation or Pulse Skipping Mode No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 0.8V Reference Allows Low Output Voltages Shutdown Mode Draws < 1A Supply Current 2% Output Voltage Accuracy Current Mode Control for Excellent Line and Load Transient Response Overcurrent and Overtemperature Protected Available in 8-Lead MSOP Package
The LTC (R)3404 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. Supply current during operation is only 10A and drops to < 1A in shutdown. The 2.65V to 6V input voltage range makes the LTC3404 ideally suited for single Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. Switching frequency is internally set at 1.4MHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications the LTC3404 can be externally synchronized from 1MHz to 1.7MHz. Burst Mode operation is inhibited during synchronization or when the SYNC/MODE pin is pulled low, preventing low frequency ripple from interfering with audio circuitry. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with the 0.8V feedback reference voltage. The LTC3404 is available in a space saving 8-lead MSOP package. For higher input voltage (11V abs max) applications, refer to the LTC1877 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation.
APPLICATIO S
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Cellular Telephones Wireless and DSL Modems Personal Information Appliances Portable Instruments Distributed Power Systems Battery-Powered Equipment
TYPICAL APPLICATIO
VIN 2.65V TO 6V 7 10F*** CER 6 1 2 47pF SYNC VIN RUN ITH GND VFB 4 3 SW 5
Efficiency vs Output Load Current
100 95
EFFICIENCY (%)
High Efficiency Step-Down Converter
4.7H* 20pF VOUT 3.3V 22F** CER
90 85 80 75
LTC3404 887k 280k
3404 TA01
*TOKO D52LC A914BYW-4R7M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN VOUT CONNECTED TO VIN FOR 2.65V < VIN < 3.3V
70 0.1
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VIN = 3.6V VIN = 4.2V VIN = 6V Burst Mode OPERATION VOUT = 3.3V L = 4.7H 1 10 LOAD (mA) 100 1000
3404 TA02
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LTC3404
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW RUN ITH VFB GND 1 2 3 4 8 7 6 5 PLL LPF SYNC/MODE VIN SW
Input Supply Voltage (VIN)...........................- 0.3V to 7V ITH, PLL LPF Voltage ................................- 0.3V to 2.7V RUN, VFB Voltages ...................................... - 0.3V to VIN SYNC/MODE Voltage .................................. - 0.3V to VIN SW Voltage ................................... - 0.3V to (VIN + 0.3V) P-Channel MOSFET Source Current (DC) ........... 800mA N-Channel MOSFET Sink Current (DC) ............... 800mA Peak SW Sink and Source Current ........................ 1.5A Operating Ambient Temperature Range (Note 2) .................................................. - 40C to 85C Junction Temperature (Note 3) ............................ 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC3404EMS8 MS8 PART MARKING LTKR
MS8 PACKAGE 8-LEAD PLASTIC MSOP
TJMAX = 125C, JA = 150C/ W
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 3.6V unless otherwise specified.
SYMBOL IVFB VFB VOVL VFB VLOADREG VIN IQ PARAMETER Feedback Current Regulated Output Voltage Output Overvoltage Lockout Reference Voltage Line Regulation Output Voltage Load Regulation Input Voltage Range Input DC Bias Current Pulse Skipping Mode Burst Mode Operation Shutdown Oscillator Frequency SYNC Capture Range Phase Detector Output Current Sinking Capability Sourcing Capability RDS(ON) of P-Channel MOSFET RDS(ON) of N-Channel MOSFET fPLLIN < fOSC fPLLIN > fOSC ISW = 100mA ISW = -100mA
q q
CONDITIONS (Note 4) (Note 4) 0C TA 85C (Note 4) - 40C TA 85C VOVL = VOVL - VFB VIN = 2.65V to 6V (Note 4) Measured in Servo Loop; VITH = 0.9V to 1.2V Measured in Servo Loop; VITH = 1.6V to 1.2V (Note 5) 2.65V < VIN < 6V, VSYNC/MODE = 0V, IOUT = 0A VSYNC/MODE = VIN, IOUT = 0A VRUN = 0V, VIN = 6V VFB = 0.8V VFB = 0V
q q q q q q q
MIN 0.784 0.74 20
TYP 4 0.8 0.8 50 0.05 0.1 - 0.1
MAX 30 0.816 0.84 110 0.2 0.5 - 0.5 6
UNITS nA V V mV %/V % % V A A A MHz kHz MHz A A
2.65 400 10 0 1.25 1.0 6 -6 20 -20 0.5 0.6 1.4 200
700 15 1 1.65 1.7 40 -40 0.7 0.8
fOSC fSYNC IPLL LPF
RPFET RNFET
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LTC3404
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 3.6V unless otherwise specified.
SYMBOL IPK ILSW ISYNC/MODE VRUN IRUN PARAMETER Peak Inductor Current SW Leakage SYNC/MODE Leakage Current RUN Threshold RUN Input Current VRUN Rising
q
CONDITIONS VIN = 3.3V, VFB = 0.7V, Duty Cycle < 35% VRUN = 0V, VSW = 0V or 6V, VIN = 6V VSYNC/MODE Rising
q
MIN 0.8 0.3 0.3
TYP 1.0 0.01 1.0 0.01 0.7 0.01
MAX 1.25 1 1.5 1 1.5 1
UNITS A A V A V A
VSYNC/MODE SYNC/MODE Threshold
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3404E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3404EMS8: TJ = TA + (PD)(150C/W)
Note 4: The LTC3404 is tested in a feedback loop which servos VFB to the balance point for the error amplifier (VITH = 1.2V). Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency.
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
95 IOUT = 100mA 90 IOUT = 10mA
100 90 80 VIN = 3.6V VIN = 4.2V EFFICIENCY (%)
85
EFFICIENCY (%)
IOUT = 1mA 80 75 70
EFFICIENCY (%)
IOUT = 300mA
IOUT = 0.1mA
65 Burst Mode OPERATION VOUT = 2.5V L = 4.7H 60 3 4 6 2 5 INPUT VOLTAGE (V)
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Efficiency vs Output Current
90 85 80 75 70 65 60 55
Efficiency vs Output Current
L = 4.7H L = 3.5H
70 60 50 40 30 20 10 PULSE SKIPPING MODE Burst Mode OPERATION VOUT = 1.8V L = 4.7H 1 10 100 OUTPUT CURRENT (mA) 1000
3404 G02
VIN = 3.6V VIN = 4.2V
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3404 G01
0 0.1
50 0.1
Burst Mode OPERATION VIN = 6V VOUT = 2.5V 1 10 100 OUTPUT CURRENT (mA) 1000
3404 G03
3
LTC3404 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current
95 VIN = 3V 90
EFFICIENCY (%) EFFICIENCY (%)
95 90 VIN = 6V 85 VIN = 4.2V 80 75 VIN = 3.6V 100
85 VIN = 3.6V 80 75 VIN = 6V 70 65 0.1 VOUT = 1.8V L = 4.7H 10 100 1 OUTPUT CURRENT (mA) 1000
3404 G04
REFERENCE VOLTAGE (V)
VIN = 4.2V
Oscillator Frequency vs Temperature
1.55 1.50 FREQUENCY (MHz) 1.45 1.40 1.35 1.30 1.25 -50 VIN = 3.6V OSCILLATOR FREQUENCY (MHz)
1.55 1.50 1.45 1.40 1.35 1.30 1.25
OUTPUT VOLTAGE (V)
-25
25 50 75 0 TEMPERATURE (C)
RDS(ON) vs Input Voltage
0.9 0.8 0.7 SYNCHRONOUS SWITCH
DC SUPPLY CURRENT (A)
RDS(ON) ()
RDS(ON) ()
0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 5 6 4 INPUT VOLTAGE (V) 3 7 8 MAIN SWITCH
4
UW
100
3404 G06
3404 G09
Efficiency vs Output Current
0.814 0.809 0.804 0.799 0.794 0.789
Reference Voltage vs Temperature
VIN = 3.6V
70 65 0.1
VOUT = 3.1V L = 4.7H 10 100 1 OUTPUT CURRENT (mA) 1000
3404 G4a
0.784 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3404 G05
Oscillator Frequency vs Supply Voltage
1.83 1.82 1.81 1.80 1.79 1.78 1.77
Output Voltage vs Load Current
125
2
4 6 SUPPLY VOLTAGE (V)
8
3404 G07
PULSE SKIPPING MODE 1.76 VIN = 3.6V L = 4.7F 1.75 200 0 600 400 LOAD CURRENT (mA)
800
3404 G08
RDS(ON) vs Temperature
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 VIN = 3V VIN = 5V SYNCHRONOUS SWITCH MAIN SWITCH
500 450 400 350 300 250 200 150 100 50 0
DC Supply Current vs Input Voltage
VOUT = 1.8V PULSE SKIPPING MODE
Burst Mode OPERATION 2 3 4 5 6 INPUT VOLTAGE (V) 7 8
3404 G11
3404 G10
LTC3404 TYPICAL PERFOR A CE CHARACTERISTICS
DC Supply Current vs Temperature
450 400
SUPPLY CURRENT (A)
SWITCH LEAKAGE (A)
300 250 200 150 100 50 0 -50 -25 Burst Mode OPERATION 50 25 75 0 TEMPERATURE (C) 100 125 VIN = 3.6V VOUT = 1.5V
SWITCH LEAKAGE (nA)
350
PULSE SKIPPING MODE
Burst Mode Operation
SW 5V/DIV
VOUT 50mV/DIV AC COUPLED IL 200mA/DIV
10s/DIV VIN = 4.2V CIN = 10F VOUT = 1.5V COUT = 22F L = 4.7H ILOAD = 30mA
Load Step Response
VOUT 100mV/DIV
IL 500mA/DIV
ITH 1V/DIV 40s/DIV VIN = 3.6V CIN = 10F VOUT = 1.5V COUT = 22F L = 4.7H ILOAD = 200mA TO 500mA PULSE SKIPPING MODE
UW
3404 G12
Switch Leakage vs Temperature
2.5 VIN = 7V RUN = 0V
1.2 1.0
Switch Leakage vs Input Voltage
RUN = 0V SYNCHRONOUS SWITCH 0.8 0.6 0.4 0.2 0 0 1 2 MAIN SWITCH
2.0
1.5
1.0
MAIN SWITCH SYNCHRONOUS SWITCH
0.5
0 - 50 - 25
0
75 50 25 TEMPERATURE (C)
100
125
5 6 3 4 INPUT VOLTAGE (V)
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3404 G13
3404 G20
Pulse Skipping Mode Operation
Start-Up from Shutdown
SW 5V/DIV
RUN 2V/DIV VOUT 1V/DIV
VOUT 10mV/DIV
IL 100mA/DIV
IL 500mA/DIV
3404 G14
500ns/DIV CIN = 10F VIN = 4.2V VOUT = 1.5V COUT = 22F L = 4.7H ILOAD = 30mA
3404 G15
40s/DIV VIN = 3.6V CIN = 10F VOUT = 1.5V COUT = 22F L = 4.7H ILOAD = 500mA
3404 G16
Load Step Response
Load Step Response
VOUT 100mV/DIV
VOUT 100mV/DIV
IL 500mA/DIV
IL 500mA/DIV
ITH 1V/DIV 40s/DIV VIN = 3.6V CIN = 10F VOUT = 1.5V COUT = 22F L = 4.7H ILOAD = 50mA TO 500mA PULSE SKIPPING MODE
ITH 1V/DIV 40s/DIV VIN = 3.6V CIN = 10F VOUT = 1.5V COUT = 22F L = 4.7H ILOAD = 50mA TO 500mA Burst Mode OPERATION
3404 G17
3404 G18
3404 G19
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LTC3404
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RUN (Pin 1): Run Control Input. Forcing this pin below 0.4V shuts down the LTC3404. In shutdown all functions are disabled drawing < 1A supply current. Forcing this pin above 1.2V enables the LTC3404. Do not leave RUN floating. ITH (Pin 2): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is from 0.5V to 1.9V. VFB (Pin 3): Feedback Pin. Receives the feedback voltage from an external resistive divider across the output. GND (Pin 4): Ground Pin. SW (Pin 5): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. VIN (Pin 6): Main Supply Pin. Must be closely decoupled to GND, Pin 4. SYNC/MODE (Pin 7): External Clock Synchronization and Mode Select Input. To synchronize with an external clock, apply a clock with a frequency between 1MHz and 1.7MHz. To select Burst Mode operation, tie to VIN. Grounding this pin selects pulse skipping mode. Do not leave this pin floating. PLL LPF (Pin 8): Output of the Phase Detector and Control Input of Oscillator. Connect a series RC lowpass network from this pin to ground if externally synchronized. If unused, this pin may be left open.
FU CTIO AL DIAGRA
BURST DEFEAT PLL LPF 8 SYNC/MODE 7
Y X
Y = "0" ONLY WHEN X IS A CONSTANT "1"
SLOPE COMP VCO OSC
0.6V 3 VFB
- +
FREQ SHIFT
gm = 0.5m VIN RUN 1
0.8V REF 0.85V SHUTDOWN
-
OVDET
+
N-CH 4 GND
3404 BD
6
-
IRCMP
+
-
+
VREF 0.8V
EA VIN SLEEP VIN
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VIN
0.8V
6 VIN
- +
0.55V
- +
EN SLEEP
-
BURST Q Q SWITCHING LOGIC AND BLANKING CIRCUIT
ICOMP
+
6
S R 2 ITH
RS LATCH
P-CH ANTISHOOTTHRU
P-CH
5 SW
LTC3404
OPERATIO
Main Control Loop The LTC3404 uses a constant frequency, current mode step-down architecture. Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each clock cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of error amplifier EA. The VFB pin, described in the Pin Functions section, allows EA to receive an output feedback voltage from an external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage, VFB, relative to the 0.8V internal reference, which in turn, causes the ITH voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. Comparator OVDET guards against transient overshoots >6.25% by turning the main switch off and keeping it off until the fault is removed. Burst Mode Operation The LTC3404 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. To enable Burst Mode operation, simply tie the SYNC/MODE pin to VIN or connect it to a logic high (VSYNC/MODE > 1.5V). To disable Burst Mode operation and enable PWM pulse skipping mode, connect the SYNC/ MODE pin to GND. In this mode, the efficiency is lower at light loads, but becomes comparable to Burst Mode operation when the output load exceeds 50mA. The advantage of pulse skipping mode is lower output ripple and less interference to audio circuitry. When the converter is in Burst Mode operation, the peak current of the inductor is set to approximately 250mA, even though the voltage at the ITH pin indicates a lower value. The voltage at the ITH pin drops when the inductor's average current is greater than the load requirement. As the ITH voltage drops below approximately 0.55V, the
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BURST comparator trips, causing the internal sleep line to go high and forces off both power MOSFETs. The ITH pin is then disconnected from the output of the EA amplifier and held a diode voltage (0.7V) above ground. In sleep mode, both power MOSFETs are held off and a majority of the internal circuitry is partially turned off, reducing the quiescent current to 10A. The load current is now being supplied solely from the output capacitor. When the output voltage drops, the ITH pin reconnects to the output of the EA amplifier and the top MOSFET is again turned on and this process repeats. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 200kHz, 1/7 the nominal frequency. This frequency foldback ensures that the inductor current has ample time to decay, thereby preventing runaway. The oscillator's frequency will progressively increase to 1.4MHz (or the synchronized frequency) when VFB rises above 0.3V. Frequency Synchronization A phase-locked loop (PLL) is available on the LTC3404 to allow the internal oscillator to be synchronized to an external source connected to the SYNC/MODE pin. The output of the phase detector at the PLL LPF pin operates over a 0V to 2.4V range corresponding to 1MHz to 1.7MHz. When locked, the PLL aligns the turn-on of the top MOSFET to the rising edge of the synchronizing signal. When the LTC3404 is clocked by an external source, Burst Mode operation is disabled; the LTC3404 then operates in PWM pulse skipping mode. In this mode, when the output load is very low, current comparator ICOMP may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. Increasing the output load slightly allows constant frequency PWM operation to resume. This mode exhibits low output ripple as well as low audio noise and reduced RF interference while providing reasonable low current efficiency. Frequency synchronization is inhibited when the feedback voltage VFB is below 0.6V. This prevents the external clock from interfering with the frequency foldback for shortcircuit protection.
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LTC3404
OPERATIO
Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC3404 is designed to operate down to an input supply voltage of 2.65V although the maximum allowable output current is reduced at this low voltage. Figure 1 shows the reduction in the maximum output current as a function of input voltage for various output voltages.
1200
MAXIMUM OUTPUT CURRENT (mA)
L = 4.7H
MAXIMUM INDUCTOR PEAK CURRENT (mA)
1000 VOUT = 3.3V 800 600 VOUT = 2.5V 400 VOUT = 1.5V 200 0
2.5
Figure 1. Maximum Output Current vs Input Voltage
APPLICATIO S I FOR ATIO
The basic LTC3404 application circuit is shown on the first page. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Value Calculation The inductor selection will depend on the operating frequency of the LTC3404. The internal nominal frequency is 1.4MHz, but can be externally synchronized from 1MHz to 1.7MHz.
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Another important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases. Therefore, the user should calculate the power dissipation when the LTC3404 is used at 100% duty cycle with a low input voltage (see Thermal Considerations in the Applications Information section). Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. As a result, the maximum inductor peak current is reduced for duty cycles > 40%. This is shown in the decrease of the inductor peak current as a function of duty cycle graph in Figure 2.
1100 VIN = 3.3V 1000 900 800 700 600
3.5
4.5 5.5 6.5 SUPPLY VOLTAGE (V)
7.5
3404 * F01
0
20
60 40 DUTY CYCLE (%)
80
100
3404 F02
Figure 2. Maximum Inductor Peak Current vs Duty Cycle
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. However, operating at a higher frequency generally results in lower efficiency because of increased internal gate charge losses. The inductor value has a direct effect on ripple current. The ripple current IL decreases with higher inductance or frequency and increases with higher VIN or VOUT.
LTC3404
APPLICATIO S I FOR ATIO
IL = V 1 VOUT 1 - OUT ( f)(L) VIN
Accepting larger values of IL allows the use of smaller inductors, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL = 0.4(IMAX). The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 250mA. Lower inductor values (higher IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Kool M (from Magnetics, Inc.) is a very good, low loss core material for toroids with a "soft" saturation characteristic. Molypermalloy is slightly more efficient at high (>200kHz) switching frequencies but quite a bit more expensive. Toroids are very space efficient, especially when you can use several layers of wire, while inductors wound on bobbins are generally easier to surface mount.
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New designs for surface mount inductors are available from Coiltronics, Coilcraft, Dale and Sumida. CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
CIN required IRMS IOMAX
[VOUT (VIN - VOUT )]1/ 2
VIN
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple VOUT is determined by:
1 VOUT IL ESR + 8 fCOUT
where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. For the LTC3404, the general rule for proper operation is: COUT required ESR < 0.25 The choice of using a smaller output capacitance increases the output ripple voltage due to the frequency dependent term but can be compensated for by using capacitor(s) of very low ESR to maintain low ripple
Kool M is a registered trademark of Magnetics, Inc.
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LTC3404
APPLICATIO S I FOR ATIO
voltage. The ITH pin compensation components can be optimized to provide stable high performance transient response regardless of the output capacitor selected. ESR is a direct function of the volume of the capacitor. Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague and Sanyo should be considered for high performance capacitors. The POSCAP solid electrolytic chip capacitor available from Sanyo is an excellent choice for output bulk capacitors due to its low ESR/size ratio. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. When using tantalum capacitors, it is critical that they are surge tested for use in switching power supplies. A good choice is the AVX TPS series of surface mount tantalum, available in case heights ranging from 2mm to 4mm. Other capacitor types include KEMET T510 and T495 series and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Output Voltage Programming The output voltage is set by a resistive divider according to the following formula: VOUT R2 = 0.8V 1 + R1
(2)
OSCILLATOR FREQUENCY (MHz)
The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 3.
0.8V VOUT 6V R2 VFB LTC3404 GND
3404 F03
R1
Figure 3. Setting the LTC3404 Output Voltage
Phase-Locked Loop and Frequency Synchronization The LTC3404 has an internal voltage-controlled oscillator and phase detector comprising a phase-locked loop. This allows the top MOSFET turn-on to be locked to the rising edge of an external frequency source. The frequency range of the voltage-controlled oscillator is 1MHz to 1.7MHz. The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the
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external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range fH is equal to the capture range, fH = fC = 300kHz and -400kHz. The output of the phase detector is a pair of complementary current sources charging or discharging the external filter network on the PLL LPF pin. The relationship between the voltage on the PLL LPF pin and operating frequency is shown in Figure 4. A simplified block diagram is shown in Figure 5.
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VPPL LPF (V)
3404 * F04
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Figure 4. Relationship Between Oscillator Frequency and Voltage at PLL LPF Pin
RLP PHASE DETECTOR 2.4V CLP PLL LPF SYNC/ MODE DIGITAL PHASE/ FREQUENCY DETECTOR
VCO
3404 F05
Figure 5. Phase-Locked Loop Block Diagram
If the external frequency (VSYNC/MODE) is greater than 1.4MHz, the center frequency, current is sourced continuously, pulling up the PLL LPF pin. When the external frequency is less than 1.4MHz, current is sunk continuously, pulling down the PLL LPF pin. If the
LTC3404
APPLICATIO S I FOR ATIO
external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLL LPF pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components CLP and RLP smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter component's CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01F. When not synchronized to an external clock, the internal connection to the VCO is disconnected. This disallows setting the internal oscillator frequency by a DC voltage on the VPLL LPF pin. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3404 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 6. 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the
POWER LOST (W)
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1 VIN = 4.2V L = 4.7H VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V Burst Mode OPERATION 0.1 0.01 0.001 0.0001 0.00001 0.1 1 10 100 LOAD CURRENT (mA) 1000
3404 F06
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Figure 6. Power Lost vs Load Current
internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss.
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LTC3404
APPLICATIO S I FOR ATIO
Thermal Considerations
In most applications the LTC3404 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3404 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 175C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3404 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(JA) where PD is the power dissipated by the regulator and qJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: T J = TA + TR where TA is the ambient temperature. As an example, consider the LTC3404 in dropout at an input voltage of 3V, a load current of 500mA, and an ambient temperature of 70C. From the typical performance graph of switch resistance, the RDS(ON) of the
CC2 LTC3404 OPTIONAL RC CC1 1 2 3 R2 R1 4 RUN ITH VFB GND CIN PLL LPF SYNC/MODE 8 7
Figure 7. LTC3404 Layout Diagram
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P-channel switch at 70C is approximately 0.7. Therefore, power dissipated by the part is: PD = ILOAD2 * RDS(ON) = 0.175W For the MSOP package, the JA is 150C/ W. Thus, the junction temperature of the regulator is: TJ = 70C + (0.175)(150) = 96C which is below the maximum junction temperature of 125C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD * ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The internal compensation provides adequate compensation for most applications. But if additional compensation is required, the ITH pin can be used for external compensation using RC, CC1 as shown in Figure 7. (The 47pF capacitor, CC2, is typically needed for noise decoupling.)
VIN 6 SW 5 L1 BOLD LINES INDICATE HIGH CURRENT PATHS
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+ + +
COUT VOUT VIN
+
-
-
3404 F07
LTC3404
APPLICATIO S I FOR ATIO
A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 * CLOAD). Thus, a 10F capacitor charging to 3.3V would require a 250s rise time, limiting the charging current to about 130mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3404. These items are also illustrated graphically in the layout diagram of Figure 7. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC3404 signal ground consists of the resistive divider, the optional compensation network (RC and CC1) and CC2. The power ground consists of the (-) plate of CIN, the (-) plate of COUT and Pin 4 of the LTC3404. The power ground traces should be kept short, direct and wide. The signal ground and power ground should converge to a common node in a starground configuration. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and signal ground. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the switching node SW away from sensitive small signal nodes.
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Design Example As a design example, assume the LTC3404 is used in a single lithium-ion battery-powered cellular phone application. The input voltage will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.3A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using equation (1), L= V 1 VOUT 1 - OUT ( f)(IL ) VIN
(3)
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Substituting VOUT = 2.5V, VIN = 4.2V, IL=120mA and f = 1.4MHz in equation (3) gives:
L=
2.5V 2.5V 1 - = 6H 1.4MHz(120mA) 4.2V
A 6.2H inductor works well for this application. For best efficiency choose a 1A inductor with less than 0.25 series resistance. CIN will require an RMS current rating of at least 0.15A at temperature and COUT will require an ESR of less than 0.25. In most applications, the requirements for these capacitors are fairly similar. For the feedback resistors, choose R1 = 412k. R2 can then be calculated from equation (2) to be:
V R2 = OUT - 1 R1 = 875.5k ; use 887k 0.8
Figure 8 shows the complete circuit along with its efficiency curve.
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LTC3404
APPLICATIO S I FOR ATIO
LTC3404 47pF 1 2 3 4 RUN ITH VFB GND PLL LPF SYNC/MODE VIN SW 8 7 6 5 6.2H* 22F** CER 887k 10F*** CER
EFFICIENCY (%)
412k
20pF
*TOKO D63LCB A920CY-6R2M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN
Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example
TYPICAL APPLICATIO S
Single Li-Ion to 2.5V/0.6A Regulator Using All Ceramic Capacitors
LTC3404 1 2 47pF 3 4 RUN ITH VFB GND PLL LPF SYNC/MODE VIN SW 8 7 6 5 4.7H* 20pF *TOKO D52LC A914BYW-4R7M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN 887k VOUT 2.5V COUT** 0.6A 22F CER VIN CIN*** 3V TO 4.2V 10F CER
3- to 4-Cell NiCd/NiMH to 1.8V/0.5A Regulator Using All Ceramic Capacitors
LTC3404 1 2 47pF 3 4 RUN ITH VFB GND PLL LPF SYNC/MODE VIN SW 8 7 6 5 4.7H* 20pF *TOKO D52LC A914BYW-4R7M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN 887k COUT** 22F CER VOUT 1.8V 0.5A CIN*** 10F CER VIN 2.7V TO 6V
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95 VIN 2.65V TO 4.2V VIN = 3V 90 VIN = 3.6V 85 VOUT 2.5V 80 VIN = 4.2V 75
3404 F08a
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VOUT = 2.5V L = 6.2H 70 0.1 10 100 1.0 OUTPUT CURRENT (mA) 1000
3404 F8b
412k
3404 TA03
698k
3404 TA04
LTC3404
TYPICAL APPLICATIO S
Externally Synchronized 2.5V/0.6A Regulator Using All Ceramic Capacitors
1 2 47pF 3 4
RUN ITH VFB GND
*TOKO D52LC A914BYW-4R7M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN
LTC3404 1 2 47pF 3 4 RUN ITH VFB GND PLL LPF SYNC/MODE VIN SW 8 7 6 5 6.2H* 20pF *TOKO D63LCB A920CY-6R2M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN 887k COUT** 22F CER VOUT 2.5V 0.3A CIN*** 10F CER VIN 2.65V TO 6V
LTC3404 1 2 47pF 3 4 RUN ITH VFB GND PLL LPF SYNC/MODE VIN SW 8 7 6 5 4.7H* VOUT 3.3V COUT** 0.5A 22F CER CIN*** 10F CER VIN 2.7V TO 6V
*TOKO D52LC A914BYW-4R7M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN VOUT CONNECTED TO VIN FOR 2.7V < VIN < 3.3V
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC3404 PLL LPF SYNC/MODE VIN SW 8 7 6 5
0.01F 10k EXT CLOCK 1.7MHz 4.7H* 20pF 887k VOUT 2.5V COUT** 0.6A 22F CER CIN*** 10F CER
VIN 3V TO 6V
412k
3404 TA04
Low Noise 2.5V/0.3A Regulator
412k
3404 TA06
3- to 4-Cell NiCd/NiMH to 3.3V/0.5A Regulator Using All Ceramic Capacitors
20pF
887k
280k
3404 TA06
15
LTC3404
TYPICAL APPLICATIO
1.58M 1% LTC1540 1 2 3 1.18M 1% 4 GND V- IN+ IN- OUT V+ REF HYS 8 7 6 5 44.2k 1% 2.37M 1%
Single Li-Ion to 2.5V/0.5A Regulator with Precision 2.7V Undervoltage Lockout
0.1F 10k 1 2 47pF 0.01F 3 4 RUN ITH VFB GND LTC3404 PLL LPF SYNC/MODE VIN SW 8 7 6 5 4.7H* 20pF *TOKO D52LC A914BYW-4R7M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***TAIYO-YUDEN CERAMIC LMK325BJ106MN 887k COUT** 22F CER VOUT 2.5V 0.6A CIN*** 10F CER VIN 2.7V TO 4.2V
PACKAGE DESCRIPTIO
0.007 (0.18) 0.021 0.006 (0.53 0.015)
0 - 6 TYP SEATING PLANE 0.193 0.006 (4.90 0.15) 0.118 0.004** (3.00 0.102)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
RELATED PARTS
PART NUMBER LTC1174/LTC1174-3.3 LTC1174-5 LTC1265 LTC1474/LTC1475 LTC1504A LTC1622 LTC1626 LTC1627 LTC1701 LTC1707 LTC1772 LTC1877 LTC1878 DESCRIPTION High Efficiency Step-Down and Inverting DC/DC Converters 1.2A, High Efficiency Step-Down DC/DC Converter Low Quiescent Current Step-Down DC/DC Converters Monolithic Synchronous Step-Down Switching Regulator Low Input Voltage Current Mode Step-Down DC/DC Controller Low Voltage, High Efficiency Step-Down DC/DC Converter Monolithic Synchronous Step-Down Switching Regulator Monolithic Current Mode Step-Down Switching Regulator Monolithic Synchronous Step-Down Switching Regulator Low Input Voltage Current Mode Step-Down DC/DC Controller High Efficiency Monolithic Step-Down Regulator High Efficiency Monolithic Step-Down Regulator COMMENTS Monolithic Switching Regulators, I OUT to 450mA, Burst Mode Operation Constant Off-Time, Monolithic, Burst Mode Operation Monolithic, IOUT to 250mA, IQ = 10A, 8-Pin MSOP Low Cost, Voltage Mode IOUT to 500mA, VIN from 4V to 10V High Frequency, High Efficiency, 8-Pin MSOP Monolithic, Constant Off-Time, IOUT to 600mA, Low Supply Voltage Range: 2.5V to 6V Constant Frequency, IOUT to 500mA, Secondary Winding Regulation, VIN from 2.65V to 8.5V Constant Off-Time, IOUT to 500mA, 1MHz Operation, VIN from 2.5V to 5.5V 1.19V VREF Pin, Constant Frequency, IOUT to 600mA, VIN from 2.65V to 8.5V 550kHz, 6-Pin SOT-23, IOUT Up to 5A, VIN from 2.2V to 10V 550kHz, MS8, VIN Up to 10V, IQ = 10A, IOUT to 600mA at VIN = 5V 550kHz, MS8, VIN Up to 6V, IQ = 10A, IOUT to 600mA at VIN = 3.3V
3404f LT/LCG 0201 4K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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412k
3404 TA08
Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.043 (1.10) MAX 0.034 (0.86) REF 0.118 0.004* (3.00 0.102) 8 76 5
0.009 - 0.015 (0.22 - 0.38)
0.0256 (0.65) BSC
0.005 0.002 (0.13 0.05)
MSOP (MS8) 1100
1
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(c) LINEAR TECHNOLOGY CORPORATION 2000

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